Hardware

IBM claims world's first sub-1 nanometer chip technology

IBM announced its first sub-1 nanometer chip technology, capable of integrating nearly 100 billion transistors on a fingernail-sized chip, doubling the transistor density of its previous generation.

Focused detail of a modern server rack with blue LED indicators in a data center.

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IBM has developed a new chip architecture that can integrate nearly 100 billion transistors on a chip the size of a human fingernail, nearly doubling the transistor density of the company’s previous generation of chip technology. This advancement is described as the 'world’s first sub-1 nanometer chip technology' for AI data centers, promising significant improvements in compute performance and energy efficiency. 'It’s not just an incremental step, it’s a meaningful leap forward,' said Jay Gambetta, director of IBM Research and IBM Fellow, during an advance media briefing. IBM’s new technology is based on a 'nanostack' architecture that vertically stacks transistors to increase density and performance without relying on physical scaling below 1 nanometer.

The company’s new chip technology is built at the 0.7-nanometer node, which it refers to as the 7 angstrom node. However, node numbers do not directly correspond to the physical dimensions of the chip features, as has been the case for decades. IBM’s nanostack architecture builds on its prior development of nanosheet transistors, which enabled the 2-nanometer chip node introduced in 2021. The basic unit of the nanostack architecture consists of two transistors stacked and bonded together, each made of three nanosheets that are 5 nanometers thick. This design allows for more transistors to be packed into the same chip space, enhancing performance and efficiency.

IBM researchers demonstrated that the nanostack architecture could provide up to 50 percent higher computing performance or 70 percent greater energy efficiency compared to its previous 2-nanometer node chips. The company introduced the nanostack transistor architecture at the 2025 IEEE Symposium on VLSI Technology and Circuits in Kyoto, Japan. Additionally, the architecture showed a 40 percent improvement in scaling for static random-access memory (SRAM), which is crucial for AI applications due to its fast but energy-intensive read and write operations. The memory improvement comes from a staggered-channel design that reduces cell height by 40 percent and allows more SRAM to be integrated into the same chip space.

Source: arstechnica

Key points

IBM announced its first sub-1 nanometer chip technology, capable of integrating nearly 100 billion transistors on a fingernail-sized chip.
IBM’s new chip technology is described as the 'world’s first sub-1 nanometer chip technology' for AI data centers.
The company’s new chip technology is built at the 0.7-nanometer node, which it refers to as the 7 angstrom node.
IBM’s nanostack architecture builds on its prior development of nanosheet transistors, which enabled the 2-nanometer chip node introduced in 2021.
The basic unit of the nanostack architecture consists of two transistors stacked and bonded together, each made of three nanosheets that are 5 nanometers thick.
IBM researchers demonstrated that the nanostack architecture could provide up to 50 percent higher computing performance or 70 percent greater energy efficiency compared to its previous 2-nanometer node chips.
The nanostack architecture showed a 40 percent improvement in scaling for static random-access memory (SRAM), reducing cell height by 40 percent.

Source: Ars Technica Read the original →

WRITTEN BY

Sam Bergstrom

AI Infrastructure & Hardware

Sam specializes in AI chips, data centers, and training infrastructure.