Hardware
XCENA Raises $135M at $570M Valuation for Memory-Optimized AI Chips
XCENA, a startup focused on memory optimization for AI, secured $135 million in Series B funding at a $570 million valuation, aiming to reduce AI infrastructure costs by improving data flow.
XCENA, a startup based in South Korea and the U.S., has raised $135 million in a Series B funding round at a $570 million valuation. The company is targeting inefficiencies in AI infrastructure by developing memory-optimized chips that bring computation closer to data storage. According to the source, the startup’s MX1 chip connects to the CPU through CXL, allowing data processing to occur near memory without the costly round trips between CPUs, GPUs, and memory. This approach could significantly reduce AI infrastructure costs, which explains investor enthusiasm. XCENA’s CEO, Jin Kim, stated that the recent rise in memory prices highlights a broader shift toward memory-centric architectures in AI. The MX1 is still a prototype, with mass production scheduled for the end of 2026 on Samsung’s foundry lines, and revenue expected to begin in 2027. The company’s ideal customers are hyperscalers spending tens of billions annually on AI infrastructure, where even small gains in memory efficiency can translate to substantial cost savings. XCENA’s closest competitors include Astera Labs and Marvell, both of which are working on next-generation memory connectivity solutions. Kim emphasized that XCENA’s vertical integration, including its own memory hierarchy and DRAM controller, sets it apart from rivals like Marvell, which relies on RISC-V cores. Seoul-based VC firms Atinum and IMM Investment co-led the Series B round, with additional funding discussions ongoing with international investors. *Source: [techcrunch](https://techcrunch.com/2026/05/29/xcena-secures-135m-at-570m-valuation-betting-on-memory-as-ais-real-bottleneck/)*
Key points
- XCENA secured $135 million in Series B funding at a $570 million valuation.
- XCENA’s MX1 chip connects to the CPU through CXL, allowing data processing near memory.
- The MX1 is a prototype, with mass production scheduled for the end of 2026.
- XCENA’s CEO, Jin Kim, stated that memory prices indicate a shift toward memory-centric AI architectures.
- XCENA’s MX1 could reduce AI infrastructure costs by minimizing data movement between CPUs, GPUs, and memory.
- XCENA’s vertical integration includes its own memory hierarchy and DRAM controller.
- XCENA’s competitors include Astera Labs and Marvell, which use RISC-V cores.