What changed
Tesla has disclosed its revamped AI accelerator roadmap, revealing that its 6th Generation inference accelerator, SI6, will deliver 80X more compute performance than the existing 4th Generation chip, HW4. The Dojo D3 training accelerator will transition from an SRAM-centric architecture to a multi-chiplet design with stacked HBM. The company has also adopted the term 'super intelligence' (SI) for its AI accelerators, renaming them with SI monikers.
What this means in practice
Tesla's SI6 inference accelerator is expected to offer 17,280 – 46,080 TOPS (trillion operations per second) or 17.28 – 46.08 POPS (quadrillion operations per second), depending on how HW4 performance is measured. This represents a significant leap in compute power compared to the current HW4, which is used in Tesla's Full Self-Driving (FSD) technology. The Dojo D3 training accelerator will use a chiplet-based design with 2.5D and 3D packaging technologies, along with stacked HBM, which is intended to increase memory capacity for large AI models. The shift from SRAM to HBM suggests Tesla is prioritizing memory scalability over SRAM-centric architectures, which are better suited for wafer-scale integration.
Limitations and availability
The supplied announcement does not specify the exact compute performance of Dojo D3, its memory capacity, manufacturing process, or development schedule. Tesla claims that Dojo D3 will be optimized for 'space, training, and scaling,' indicating a more conventional architecture rather than wafer-scale integration. The SI6 is expected to be available in 2029 – 2030, with Samsung Foundry manufacturing it using a 2nm-class process technology. The Dojo D3 is also set to be optimized for extraterrestrial deployments, likely including radiation hardening for select SKUs.
